The present invention relates to asynchronous semiconductor memory, and more specifically relates to particular asynchronous semiconductor memory of the type designed according to standard cell system.
FIG. 1 shows a circuit diagram of the ideal asynchronous semiconductor memory devised by this inventor. The asynchronous semiconductor memory does not utilize an external clock signal but generates a clock signal internally. When a signal is transited at an address input terminal 1, that signal is inputted into an input D of a latch circuit 9 and into exclusive-OR gate (EX-OR 3) in the asynchronous semiconductor memory. At this time, since a clock input CK of the latch circuit 9 is a High level, the latch circuit 9 is in data-through state. Therefore, an address signal inputted into the latch circuit 9 is transmitted through its output Q to a delay circuit 2. Since inputs of the EX-OR 3 are from the address input terminal 1 and from the delay circuit 2, an output of the EX-OR 3 which detects transition between an old address signal and a new address signal has High level. The delay circuit 2 sets a delay time of reading and writing of RAM cell data. When a signal delayed by the delay time is inputted into the EX-OR 3, since input data coincide with each other, the output of the EX-OR 3 becomes Low level. When a gate of Nchannel (Nch)-transistor 4 becomes High level, the Nchannel (Nch)-transistor 4 turns ON and drain voltage of the Nch-transistor 4 is changed from High level to Low level to generate an internal clock at a node N.sub.1. The internal clock is input to a clock signal input in the latch circuit 9. When the internal clock is at Low, the address signal is latched. Until the internal clock turns to High, the address signal inputted from the address input terminal 1 is blocked.
A time interval from change of a given address signal to generation of the internal clock (Low level) corresponds to a time interval during which another address signal can be read (skew). In the prior art, this skew time interval is fixed according to a delay amount of the circuit. There has been proposed no skew control circuit effective to vary the skew time interval according to timing of peripheral system.
In an address detecting circuit of the conventional asynchronous semiconductor memory as described above, since the skew time interval is fixed from the transition of address signal for selecting a desired word line in order to select a particular RAM cell until the generation of internal clock, the conventional memory has drawback that it is necessary to set timing of peripheral system within the skew time interval of the asynchronous semiconductor memory.